Static random access memory (SRAM) conventionally uses a six-transistor (6-T) memory cell that includes cross-coupled inverters that drive a bit node and bit complement node. To provide a second access port, two additional transistors are added to the 6-T memory cell to form an 8-T dual-port SRAM cell. FIG. 1 shows the resulting 8-T dual-port SRAM cell 100. Transistors Q1, Q2, Q3, and Q4 form cross-coupled inverters that drive a DATA node 105 and a DATA complement (DATAb) node 110. A first read/write access port A to nodes 105 and 110 is formed by access transistors Q5 and Q6 as driven by a word line A (WLA). Similarly, a second read/write access port B to nodes 105 and 110 is formed by access transistors Q7 and Q8 as driven by a word line B (WLB). Each word line is asserted during a read or write operation by a corresponding word line driver 115.
When word line WLA is asserted, access transistor Q5 turns on to couple a true bit line A (BLA) to DATA node 105. Similarly, with WLA being asserted, access transistor Q6 turns on to couple a complement bit line A (BLAb) to complement data node DATAb 110. Conversely, assertion of word line B (WLB) turns on access transistors Q7 and Q8 to couple a true bit line B (BLB) to node 105 and to couple a complement bit line B (BLBb) to complement data node 110. As known in the SRAM arts, each bit line pair is sensed by a corresponding sense amplifier 120 during read operations as driven by a read enable signal (RdEn). When neither a read nor a write operation is active, the bit line pairs are pre-charged by a corresponding precharge network 125. In a write operation, the bit line pairs are driven by a corresponding write driver 130 as enabled by a write enable signal (WrEn).
Read and write operations on the dual access ports may be performed asynchronously. While it is considered illegal to attempt to write to cell 100 through both ports simultaneously, it is allowed that one port may write to the cell while the remaining port is reading from the cell. In such circumstances, the read operation may return an indeterminate value. However, it is desirable that a write operation at one access port succeed consistently despite the existence of concurrent read operation at the remaining access port. Thus, a write operation on one access port should succeed in spite of a wide variety of possible states for the remaining access port, which ranges from an un-accessed state to a fully-developed read access state. In that regard, the fully-developed read access state may be of the opposite polarity with regard to the bit being driven by the write operation.
This opposite polarity of a read operation on one port may affect the write operation on the remaining port. For example, if data node 105 is storing a logical high state (DATA=1) whereas complement data node 110 is storing a logical low state (DATAb=0), the stored data states will oppose a write operation occurring at access port B that is attempting to “flip” the memory cell—in other words, a write operation that attempts to bring data node 105 low and complement data node 110 high. In such a scenario, word line A (WLA) will be asserted in conjunction with the read operation at port A after the release of the pre-charge on bit lines BLA and BLAb. Bit line BLAb will then be pulled low through transistor Q2. If one neglects the effect of sense amplifier 120, bit line BLA will be held at the supply voltage VCC minus the threshold voltage for Q5. However, many sense amplifiers utilize positive feedback that will assist in pulling bit line BLAb low and bit BLA high more quickly than just through the discharge through transistor Q2.
To begin the write operation at port B, word line B (WLB) goes high after the release of the pre-charge on bit lines BLB and BLBb. Write driver 130 will then pull bit line BLB low while maintaining complement bit line BLBb high. Bit line BLB low in turn pulls DATA node 105 low through transistor Q8. The threshold voltage drop Vt across transistor Q7 prevents high bit line BLBb from charging DATAb node 110 fully high. DATAb node 110 is instead charged high when low DATA node 105 turns on transistor Q1. Conversely, as DATAb node 110 goes high, transistor Q4 is turned on, which pulls DATA node 105 fully to ground. The minimum time necessary to complete the write operation at port B is affected by the read operation that has yet to be completed at port A. In that regard, transistor Q1 must pull DATAb node 110 and bit line BLAb (through transistor Q6) sufficiently high to prevent the read operation from writing the old bit back into node DATAb 110 once the write operation at port B ceases. Transistors Q1 and Q6 are relatively weak with regard to the heavily-loaded bit line BLAb so that charging bit line BLAb in this fashion requires some time. The write operation time must thus be increased to ensure that opposing read operations are countered in this fashion.
Several approaches have been developed to address the conflict between simultaneous read and write operations in dual-port memories. For example, one approach uses logic to ensure that write operations have priority over reads. The logic monitors whether write operations exist on any given row in the memory. If a write operation is detected at one port for a dual-port memory cell, the logic prevents any read operations on the opposing port by pulling the corresponding word line low. In this fashion, the read bit lines are isolated from the memory cell, which reduces the amount of time necessary to complete the write operation on the opposing port since none of the isolated read bit lines need to be charged in conjunction with the operation charging the memory cell node. But such a logic approach suffers from the requirement of adding the necessary logic itself and its associated routing. Moreover, the approach suffers from disturbing a read operation whenever a simultaneous write operation occurs.
In another technique, the SRAM cell itself is redesigned with more robust cell transistors and write-driver circuitry. But such an approach increases die cost due to the necessary die area that must be allotted to the larger transistors. In addition, the larger cell transistors increase capacitance and thus load the bit-lines undesirably.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.